FIG. 1(c) is a cross-sectional view of an example of a conventional semiconductor device shown in Japanese Unexamined Patent Publication No. SHO 63-15475 (JP-A-63 15 475). On a semiconductor substrate I, a buffer layer 2 and a semiconductor active layer 3 are stacked, and a gate electrode 4 having a length Lg is disposed in a recess 5 formed in the surface of semiconductor active layer 3.
The semiconductor device having a cross-sectional structure shown in FIG. 1(c) may be made in the following manner. As shown in FIG. 1(a), buffer layer 2 and semiconductor active layer 3 are stacked. Recess 5 is then formed in the surface of active layer 3. A source electrode 6 and a drain electrode 7 are then disposed on active layer 3. Then, a resist layer 8 having an opening 7a therein at a location corresponding to recess 5 is formed. After that another resist layer 9 having an opening 10 extending to recess 5 is formed. The width t.sub.1 of the opening 10 determines the length Lg of completed gate electrode 4 shown in FIG. 1(c). After that a resist layer 12 having an opening 11 is formed.
A gate metal, such as aluminum (A1), forming gate electrode 4 is vapor deposited from above the structure shown in FIG. 1(a), so that the gate metal is deposited within openings 10 and 11 as shown in FIG. 1(b), whereby T-shaped gate electrode 4 is formed. A gate metal layer 13 is disposed on the resist layer 12.
Gate metal layer 13 and resist layers 12, 9 and 8 are removed off, and the semiconductor device having gate electrode 4 is completed. The details of manufacturing steps of this device are described in Japanese Unexamined Patent Publication No. SHO 63-15475 (JP-A-63 15 475).
According to the above-described conventional manufacturing method, however, when the gate metal is vapor deposited, the metal is also deposited on upper portions of opening 10 in resist layer 9 as indicated by a reference numeral 14 in FIG. 1(b), to thereby making the upper end of opening 10 narrower and narrower as the vapor deposition advances. This causes the amount of the metal passing through opening 10 to decrease gradually so that a leg portion 15 of gate electrode 14 disposed in recess 5 becomes tapered as shown in FIG. 1(b) and 1(c). Sometimes leg 15 may be broken when it is tall and, therefore, there is a limitation on the height of the gate electrodes. Then, the spacing between the head 16 of gate electrode 4 and semiconductor active layer 3 cannot be made larger. This means that the capacitance between head 16 of gate electrode 4 and semiconductor active layer 3 cannot be made smaller than a certain value, which is one of the limits on improvement of the operating speed of ICs.
One may contemplate increasing the gate length Lg so as to permit formation of a thicker upper end of leg 15 of gate electrode 4. One of factors determining characteristics, such as a noise factor (NF), of a FET is the gate length Lg. It is known that as the gate length Lg increases, the noise factor NF decreases. Therefore the gate length Lg cannot be increased much.
According to the above-referenced conventional technique, gate electrode 4 is formed by vapor depositing a gate metal, and, therefore, the height, a, of head 16 and the height, b, of leg 15 should be equal. Accordingly, in case that there is a restriction on the height of gate electrode 4, it is not possible to form a longer leg with a shorter head. Thus, the height of leg 15 cannot exceed a prescribed value, and, therefore, electrostatic capacitance between head 16 of gate electrode 14 and semiconductor active layer 3 cannot be made smaller than a prescribed value.
Japanese Unexamined Patent Publication No. SHO 61-59881 (JP-A-61 59 881) shows another example of a method of making a semiconductor device having a T-shaped gate electrode. According to this method, as shown in its FIG. 6, a gate electrode can be disposed at a location closer to a source. However, the gate electrode is formed by vapor-depositing a gate metal as in JP-A-63 15475, and, therefore, this prior art also has the same problem.
Another examples of prior art techniques for making a semiconductor device having a T-shaped gate electrode are shown in Japanese Unexamined Patent Publication No. HEI 2-105423 (JP-A-21 05 423) and No. HEI 2-105424 (JP-A-21 05 424). According to these techniques, a gate electrode having an expanded head is located on the drain electrode side so as to minimize source-gate capacitance. However, in these techniques, too, the gate electrode is formed by vapor depositing a gate electrode metal as in the previously described prior art techniques. These techniques also have the same problem.
An object of the present invention is to provide a semiconductor device having a T-shaped gate electrode having a ratio of the height of a leg of the gate electrode to the total height of the gate electrode greater than 1/2, and a method of making such a semiconductor device.
Another object of the present invention is to provide a semiconductor device having a T-shaped gate electrode having a leg of which the cross-sectional area in planes parallel to the surface of a semiconductor substrate, i.e. the transverse cross-sectional area, is substantially constant along the entire height, and a method of making such a semiconductor device.